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CS5305 Three-Phase Synchronous Switching Step-Down Controller with Single Wire Current Sharing
The CS5305 provides a low-cost, single-controller solution for the low-voltage, high-current power needs of next-generation workstation and server processors. This IC provides high accuracy and the industry's fastest transient response, reducing the need for large banks of output capacitors and providing the most compact, reliable, and economical power supply. Since each phase's output voltage and current feed back to develop the PWM ramp signal (enhanced V2TM control), the CS5305 shares output current accurately between phases. Accurate current sharing means that the power supply design does not need to use power components rated to handle mismatched current per phase. The enhanced V2 control compensates for variations in both line and load. The IC's built-in single wire current sharing capability allows easy paralleling of multiple Voltage Regulator Modules (VRMs) based on the CS5305. The paralleled VRMs use a shared bus to provide high current and high reliability to multiple microprocessor workstations or servers. The CS5305 meets VRM 9.x specifications with its Power Good, Enable, Differential Remote Sense, and single-wire Current Share features. The product fits server and workstation VRMs, and can be used to power Embedded Processors. The IC provides the simplest, lowest-cost solution for any low voltage, high current power supply. Features Enhanced V2 Control Method VRM 9.x Compatible VID Codes Lossless Inductor Current Sensing Single Wire Active Current Sharing Between Converters Auto Master-Slave Current Share Control Method Programmable 200 to 800 kHz Switching Frequency Programmable Adaptive Voltage Positioning Differential Remote Sense Pulse-by-Pulse Current Limit Master Hiccup Overcurrent Protection through Single Wire Share Bus * 5-Bit DAC with 1% Tolerance * ENABL Input * VRM 9.x-Compliant Power Good Output * Active Current Sharing During Soft Start
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28 CS5305 AWLYYWW 1 SO-28L DW SUFFIX CASE 751F 1
28
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
PIN CONNECTIONS
1 OCSET ROSC ENABL CS1 CS2 CS3 CSREF IFB IOUT SHARE SCOMP VDRP VFB COMP 28 GND GATE1 GATE2 GATE3 DRVON VCC SGND PWRGDS VID0 VID1 VID2 VID3 VID4 PWRGD
* * * * * * * * * *
ORDERING INFORMATION
Device CS5305GDW28 CS5305GDWR28 Package SO-28L SO-28L Shipping 27 Units/Rail 1000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2001
1
October, 2001 - Rev. 6
Publication Order Number: CS5305/D
CS5305
APPLICATION DIAGRAMS
270 nH
+12 V 5.6 V 220 k
100 F x5 BAS40LT1 NTD 4302 x2 470 nH
0.1 F
6.2 V
20
1 F
ENABLE
NCP5351
PGND VCC GL
.47 F
BST GH
SWN
IN
VOUT
10 F x3
GND
2.2 F
NTD 4302 x2
28.7 k
20 k
BAS40LT1 NTD 4302 x2
BST GH
ROSC ENABL CS1 CS5305 47 nF 3.9 k CS2 CS3 CSREF IFB 12 k 3k .01 F 22 nF 91 k 47 nF x3 0.1 F 17 k IOUT SHARE SCOMP VDRP VFB COMP
GATE1 GATE2 GATE3 DRVON VCC SGND VID0 VID1 VID2 VID3 VID4 PWRGD
1 F
ENABLE
NCP5351
PGND VCC GL
SWN
IN
ENABLE
.47 F
OCSET
GND
PWRGDS
NTD 4302 x2
BAS40LT1 NTD 4302 x2
BST GH
1 F
ENABLE
SWN
IN
.47 nF
NCP5351
PGND VCC GL
220 220 12 k x3
NTD 4302 x2
GND SENSE POWERGOOD VOUT SENSE SHARE VID4 VID3 VID2 VID1 VID0
60.4 k
Figure 1. VRM 9.0, 60 A Converter http://onsemi.com
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CS5305
5.0 V 1.5 k 12 V ENABLE VID0 VID1 VID2 VID3 VID4 12 V VOUT SENSE VOUT VOUT GND POWERGOOD
ENABLE VID0 GND GND SENSE VID1 VID2 POWERGOOD VID3 SHARE VID4
12 V
VOUT SENSE VOUT
ENABLE GND VID0 GND SENSE VID1 VID2 POWERGOOD VID3 SHARE VID4
* Inductors & Resistors represent distribution impedances.
Figure 2. Two-Converter System with Sharing MAXIMUM RATINGS*
Rating Operating Junction Temperature Storage Temperature Range ESD Susceptibility (Human Body Model) Thermal Resistance, Junction-to-Case, RJC Thermal Resistance, Junction-to-Ambient, RJA JEDEC Moisture Sensitivity Lead Temperature Soldering: 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) Note 1. Value 150 -65 to 150 2.0 15 75 Level 5 230 peak Unit C C kV C/W C/W - C
MAXIMUM RATINGS
Pin Number 1 2 3 4-6 7 8 9 10 11 12 13 14 15 Pin Symbol OCSET ROSC ENABL CS1-3 CSREF IFB IOUT SHARE SCOMP VDRP VFB COMP PWRGD VMAX 7.0 V 7.0 V 16 V 7.0 V 7.0 V 7.0 V 7.0 V 16 V 7.0 V 7.0 V 7.0 V 7.0 V 16 V VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V ISOURCE 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 10 mA 50 mA 1.0 mA 1.0 mA 1.0 mA 10 mA 1.0 mA ISINK 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 10 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 20 mA
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CS5305
MAXIMUM RATINGS (continued)
Pin Number 16-20 21 22 23 24 25-27 28 Pin Symbol VID4-VID0 PWRGDS SGND VCC DRVON GATE 3-1 GND VMAX 16 V 7.0 V 0.3 V 16 V 7.0 V 16 V N/A VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V N/A ISOURCE 1.0 mA 1.0 mA 1.0 mA N/A 10 mA 0.1 A, 1.0 s; 25 mA DC 0.4 A, 1.0 s; 100 mA DC ISINK 1.0 mA 1.0 mA 1.0 mA 0.4 A, 1.0 s 100 mA DC 1.0 mA 0.1 A, 1.0 s 25 mA DC N/A
ELECTRICAL CHARACTERISTICS (0C < TA < 70C; 0C < TJ < 125C; 9.5 V < VCC < 14 V; CGATEX = 100 pF, CCOMP = 0.01F, CSCOMP = 0.01F, CVCC = 0.1F, RROSC = 32.4 k, RSHARE = 60.4 k, V(OCSET) = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter Test Conditions Min Typ Max Unit
Voltage Identification DAC (0 = Connected to GND, 1 = Open (Pulled-up to internal 3.3 V) or Pulled-up to external voltage 3 13 V) Accuracy (all codes) VID code - 125 mV VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Connect VFB to COMP, SGND < 55 mV, Measure COMP - SGND VID Maximum Voltage DRVON < 1.0 V, GATEX < 1.0 V 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 0.965 0.990 1.015 1.040 1.064 1.089 1.114 1.139 1.163 1.188 1.213 1.238 1.263 1.287 1.312 1.337 1.361 1.386 1.411 1.436 1.460 1.485 1.510 FAULT Mode 0.975 1.000 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 0.985 1.010 1.035 1.061 1.086 1.111 1.136 1.162 1.187 1.212 1.237 1.263 1.288 1.313 1.338 1.364 1.389 1.414 1.439 1.465 1.490 1.515 1.540 V V V V V V V V V V V V V V V V V V V V V V V V 1.0 %
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CS5305
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 9.5 V < VCC < 14 V; CGATEX = 100 pF, CCOMP = 0.01F, CSCOMP = 0.01F, CVCC = 0.1F, RROSC = 32.4 k, RSHARE = 60.4 k, V(OCSET) = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter Test Conditions Min Typ Max Unit
Voltage Identification DAC (0 = Connected to GND, 1 = Open (Pulled-up to internal 3.3 V) or Pulled-up to external voltage 3 13 V) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850 VID4, VID3, VID2, VID1, VID0 0 V < VID4, VID3, VID2,VID1, VID0 < 3.3 V 1.0 M to GND SGND < 55 mV, All DAC Codes 1.535 1.560 1.584 1.609 1.634 1.658 1.683 1.708 1.00 25 2.5 10 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.25 50 2.7 20 1.566 1.591 1.616 1.641 1.667 1.692 1.717 1.742 1.5 100 3.0 40 V V V V V V V V V k V A
Input Threshold Input Pull-up Resistance Pull-up Voltage SGND Bias Current Power Good Output Upper Threshold Lower Threshold
Force PWRGDS-SGND SGND < 55 mV Force PWRGDS-SGND SGND < 55 mV
1.876 (-5%) 0.95 x (VID - 125 mV) or -2.6% from nominal PWRGD Threshold
1.975 0.975 x (VID - 125 mV)
2.074 (+5%) VID - 125 mV or +2.6% from nominal PWRGD Threshold
V V
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
VID3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1
VID2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1
VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0.926 0.950 0.974 0.998 1.021 1.045 1.069 1.093 1.116 1.140 1.164 1.188 1.211 1.235 1.259 1.283 1.306 0.951 0.975 1.000 1.024 1.048 1.073 1.097 1.122 1.146 1.170 1.195 1.219 1.243 1.268 1.292 1.316 1.341 0.975 1.000 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 V V V V V V V V V V V V V V V V V
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CS5305
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 9.5 V < VCC < 14 V; CGATEX = 100 pF, CCOMP = 0.01F, CSCOMP = 0.01F, CVCC = 0.1F, RROSC = 32.4 k, RSHARE = 60.4 k, V(OCSET) = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter Power Good Output 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VCC = 14 V, PWRGDS = 1.4 V PWRGDS low to PWRGD low PWRGDS = 1.0 V, IPWRGOOD = 4.0 mA 1.330 1.354 1.378 1.401 1.425 1.449 1.473 1.496 1.520 1.544 1.568 1.591 1.615 1.639 - 50 - 1.365 1.389 1.414 1.438 1.463 1.487 1.511 1.536 1.560 1.584 1.609 1.633 1.658 1.682 - 250 0.15 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.0 600 0.4 V V V V V V V V V V V V V V A s V Test Conditions Min Typ Max Unit
Switch Leakage Current Delay Output Low Voltage Voltage Feedback Error Amplifier VFB Bias Current Comp Source Current Comp Sink Current Transconductance Output Impedance Open Loop DC Gain Unity Gain Bandwidth PSRR @ 1.0 kHz COMP Max Voltage COMP Min Voltage COMP Discharge Threshold Hiccup Latch Discharge Current
Note 2. COMP = 0.5 V to 2.0 V, VFB = 1.6 V COMP = 0.5 V to 2.0 V, VFB = 1.0 V -10 A < ICOMP < +10 A, Note 3. Note 3. Note 3. COMP = 0.01 F, Note 3. Note 3. VFB = 0 V VFB = 1.6 V - CSx - CSREF = .05 V, OCSET = 0.1 V, COMP = 0.5 V -
9.5 15 15 - - 60 - - 2.4 - 0.15 2.0
10.3 30 30 32.0 2.5 95 50 70 2.7 0.1 0.2 5.0
11.5 60 60 - - - - - - 0.2 0.25 10
A A A mmho m dB kHZ dB V V V A
Hiccup Charge / Discharge Ratio
4.5
6.0
7.5
-
2. The VFB Bias Current changes with the value of ROSC per Figure 5. 3. Guaranteed by design. Not tested in production.
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CS5305
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 9.5 V < VCC < 14 V; CGATEX = 100 pF, CCOMP = 0.01F, CSCOMP = 0.01F, CVCC = 0.1F, RROSC = 32.4 k, RSHARE = 60.4 k, V(OCSET) = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter Voltage Feedback Error Amplifier SHARE Fault Discharge Current SHARE = 3.5 V, COMP = 0.5 V, CSx = CSREF = 0 V, OCSET = 0.5 V 0.3 2.5 5.0 mA Test Conditions Min Typ Max Unit
Enable Input Threshold Voltage Pull-up Voltage Input Pull-up Resistance PWM Comparators Minimum Pulse Width Measured from CSx to GATEx, VFB = CSREF = 0.5 V, COMP = 0.5 V, 60 mV step on CSx; measure at GATEx = 1.0 V Measured from CSREF to GATEx, COMP = 2.1 V, CSx = CSREF = 0.5 V, CSREF stepped from 1.2 V - 2.0 V CSx = CSREF = VFB = 0 V, measure V(COMP) when GATEx switch high CSx = CSREF = VFB = 0 V, measure V(COMP) when GATEx switch high, Note 4. - 75 220 ns Monitor DRVON 1 M to GND - 1.12 2.5 25 1.25 2.7 50 1.38 3.0 100 V V k
Transient Response Time
-
100
150
ns
Channel Start-up Offset
0.34
0.6
0.75
V
Channel Start-up Offset Mismatch Gates High Voltage Low Voltage Rise Time GATE Fall Time GATE Oscillator Switching Frequency Switching Frequency Switching Frequency ROSC Voltage Phase Delay
-5.0
-
5.0
mV
IGATEx = 1.0 mA IGATEx = 1.0 mA 0.8 V < GATE < 2.0 V, VCC = 10 V 2.0 V > GATE > 0.8 V, VCC = 10 V
2.25 - - -
2.5 0.2 15 15
3.0 0.4 30 30
V V ns ns
ROSC = 32.4 k ROSC = 63.4 k, Note 4. ROSC = 16.2 k, Note 4. Note 4. -
300 150 600 0.90 90
400 200 800 1.00 120
500 250 1000 1.10 150
kHz kHz kHz V deg
4. Guaranteed by design. Not tested in production.
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CS5305
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 9.5 V < VCC < 14 V; CGATEX = 100 pF, CCOMP = 0.01F, CSCOMP = 0.01F, CVCC = 0.1F, RROSC = 32.4 k, RSHARE = 60.4 k, V(OCSET) = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter Current Sense Amplifiers CSREF Input Bias Current CSx Input Bias Current Sense Amp Gain CSREF = CSx = 0 V CSREF = CSx = 0 V CSREF = 0 V, CSx = 0.05 V, Measure V(COMP) when GATEx switches high 0 (CSx - CSREF) 50 mV, Note 5. Note 5. Note 5. VFB = CSREF = 0.5 V, COMP = 2.0 V, Measure CSx - CSREF when GATEx goes low OCSET = 0 V OCSET / R (CSx - CSREF), OCSET = 0.6 V, Monitor DRVON < 1.0 V CSREF = 1.1 V, CSx = 1.0 V, pulse CSx to 1.16 V, Note 5. - - .95 0.3 0.1 1.06 3.0 1.0 1.17 A A V/V Test Conditions Min Typ Max Unit
Mismatch Common Mode Input Range Bandwidth Single Phase Pulse by Pulse Current Limit
-3.0 0 - 80
- - 7.0 90
3.0 2.0 - 100
mV V MHz mV
OCSET Input Bias Current Current Sense Input to OCSET Gain Current Limit Filter Slew Rate Adaptive Voltage Positioning VDRP Output Voltage to DACOUT Offset Maximum VDRP Voltage
- 3.4
0.1 3.7
1.0 4.0
A V/V
2.0
5.0
13
mV / s
CSx = CSREF, VFB = COMP, Measure VDRP - COMP CSx - CSREF = 50 mV, VFB = COMP, Measure VDRP - COMP CSx - CSREF = 50 mV, VFB = COMP, Measure VDRP - COMP CSx - CSREF = 50 mV, VFB = COMP, VDRP = 1.5 V
-30 500
2.0 560
60 620
mV mV
Current Sense Amp to VDRP Gain VDRP Source Current
3.4
3.7
4.0
V/V
1.0
7.0
14
mA
SHARE Current Sense Amplifier IFB Input Bias Current Input Offset Voltage Common Mode Input Range Output Current Gain Output Unity Gain BW IFB = 0 V Note 5. Note 5. IOUT = 0 V, CSx = 0.667 V, CSREF = 0.5 V Note 5. Note 5. - -5.0 0 1.0 - - 0.2 0 - 10 120 5.0 1.0 5.0 2.0 22 - - A mV V mA dB MHz
5. Guaranteed by design. Not tested in production.
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CS5305
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 9.5 V < VCC < 14 V; CGATEX = 100 pF, CCOMP = 0.01F, CSCOMP = 0.01F, CVCC = 0.1F, RROSC = 32.4 k, RSHARE = 60.4 k, V(OCSET) = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter SHARE Bus SHARE Amplifier Offset Voltage SHARE Amplifier Source Current SHARE Amplifier Max Voltage SHARE Fault Threshold SHARE OK Threshold SHARE Fault Hysteresis SHARE Fault Output Voltage SHARE Fault Output Current SHARE Full Load Accuracy SHARE Short Circuit Current SHARE Fault Short Circuit Current Current SHARE Adjust Amplifier Transconductance from IOUT to SCOMP Gain from IOUT to COMP Maximum SCOMP source current Maximum SCOMP sink current Unity Gain BW MOSFET Driver Enable Pull-Up Voltage DRVON Source Current DRVON Pull Down Resistor General Electrical Specifications VCC Disable Current UVLO Start Threshold UVLO Stop Threshold UVLO Hysteresis VCC Operating Current ENABLE = 0 V (no switching) COMP charging, DRVON > 1.0 V Gates not switching, COMP discharging, DRVON < 1.0 V Start - Stop ENABLE Open - 8.5 7.5 0.8 - 30 9.0 8.0 1.0 22 60 9.5 8.5 1.2 30 mA V V V mA DRVON Floating DRVON = 1.5 V DRVON = 1.5 V, ENABL = 0 V, R = 1.5 V / I(1.5 V) 4.5 .5 35 5.5 3.0 70 6.0 6.5 140 V mA k 0 < IOUT < 2.0 V, 0 < SCOMP < 2.0 V Note 6. SCOMP = 1.5 V SCOMP = 1.5 V C(SCOMP) = TBD, Note 6. 23 30 15 15 30 40 50 30 30 56 53 140 60 60 100 A / V mA / V A A Hz SHARE = 3.8 V CSREF = 0.5 V, CSx = 0.52 V, IOUT / FB Divider = 22 k/3.0 k V(IOUT) = 2.0 V, SHARE = GND CSREF = 0.5 V, CSx = 0.6 V Measure V(SHARE) - V(IOUT), 0 < IOUT < 2.0 V IOUT = 2.1 V, SHARE = 2.0 V IOUT = 3.5 V, TA = 25C DRVON < 1.0 V, TA = 25C DRVON > 1.0 V - - 20 1.0 2.65 3.2 2.0 1.0 3.8 1.2 1.7 1.0 2.0 40 7.5 2.80 3.4 2.3 1.15 4.25 2.0 1.95 17 19 60 24 3.20 3.7 2.5 1.3 4.7 2.5 2.2 28 30 mV mA V V V V V mA V mA mA Test Conditions Min Typ Max Unit
6. Guaranteed by design. Not tested in production.
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CS5305
PACKAGE PIN DESCRIPTION
Package Pin Number SO-28L 1 2 3 4-6 7 8 9 10 11 12 Pin Symbol OCSET ROSC ENABL CS1-3 CSREF IFB IOUT SHARE SCOMP VDRP Pin Name Over-Current Set Oscillator Frequency Adjust Enable Input Current Sense Inputs Current Sense Reference Share Current Amp Inverting Input Share Current Amp Output Share Bus Share Compensation Current Sense Output for AVP Voltage Feedback Function Resistor divider from ROSC to GND programs the threshold of the hiccup over-current protection. Resistance to GND programs the oscillator frequency. It also programs the VFB bias current shown in Figure 5. TTL-Compatible logic input with 50 k internal pull-up resistor to 3.3 V. A logic low puts the IC in FAULT mode. Non-inverting inputs to the current sense amplifiers. Inverting input to the current sense amplifiers, and fast feedback input to the PWM comparator. Inverting input to share current amp. Connect resistor divider between IOUT, IFB, and IC GND pin 28 to program Share Current Amp gain. Share current amplifier output and input to share adjust amplifier. Connect with other modules for single-wire current sharing. Connect compensation network to stabilize share loop. The offset of this pin above the DAC voltage is proportional to the output current. Connect a resistor from this pin to VFB to program the AVP voltage or leave this pin open for no AVP. Error Amp inverting input. Input bias current used to program AVP light load offset via resistor connected to converter output voltage. Short VFB to the converter output voltage for no AVP. Provides loop compensation. Also used to control Softstart and Fault timing.
13
VFB
14
COMP
Error Amp Output and PWM Comparator Input Power Good Output Voltage ID DAC Inputs Power Good Sense Reference Ground Supply Input Driver Enable FET Driver Outputs Ground
15 16-20 21 22 23 24 25-27 28
PWRGD VID4-VID0 PWRGDS SGND VCC DRVON GATE 3-1 GND
Open collector output goes low when VFB is out of regulation. User must externally limit current into this pin to less than 20 mA. Programs Output Voltage. 50 k internal pull-up resistors to 3.3 V. Provides remote output voltage sensing. Ground connection for the DAC. Provides remote sensing of ground at the load. IC Power Supply Input. Logic High enables outputs of compatible MOSFET Driver ICs. Low turns all MOSFETs OFF. Pin driven from internal 5.5 V; 70 k internal resistor to GND. PWM Signal Input to external MOSFET Gate Driver ICs. IC Power Supply Return; connected to IC substrate.
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VCC + VCC FAULT PWM1 Comparator - + PWM1 Latch R Reset Dominant PGND + - OC Comparator S Reset Dominant - + CO1F 0.33 V CO1 ILIM1 Comparator S
Start Stop
-
UVLO Comparator
ENABL ENABLE Comparator
- +
OCSET
50 k + - R SHARE Fault - + CO2F CO2 + - Discharge Comparator - + VID = 11111 ? DAC DAC OUTPUT
* 0.975 V
VID0 VID1 VID2 VID3 VID4 0.2 V - - + 3.1 V 2.1 V Error Amp - + 1.975 V FAULT - + + - 0.6 V CO3F CO3 - +
Start Stop
ILIM2 Comparator 0.33 V
S
SGND
COMP Reset
AVP Amp + SHARE Fault Comparator
Reset Dominant
Reset Dominant
CS5305
PWRGD
Delay
CS2 CO2F x3.7 - CO3 + CO3F SHARE Current Sense Amp + - -
x3.7 - CO2 + SHARE Bus Amp + - +
x1 - +
SHARE Adjust Amp + - 30 mV - + 3.3 V
CS3
IFB
IOUT
SHARE SCOMP
VFB
COMP
- +
x1 - +
- +
Figure 3. Block Diagram
PWRGDS
CSREF x3.7 - CO1 + SHARE Fault CO1F 3.8 V
CS1
x1 - +
IBIAS
- +
- +
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FAULT IDISCHG
- +
VDRP
- +
- +
1.25 V - + 3.3 V
- +
- + 9.0 V 8.0 V
3.3 V
50 k
GATE1
OC Filter
PWM2 Comparator - +
PWM2 Latch R
VCC GATE2 PGND
PWM3 Comparator - + + -
PWM3 Latch R
VCC GATE3 PGND ILIM3 Comparator 0.33 V S 5.5 V DRVON 70 k
11
OSCILLATOR Current Source Generator PULSEOUT1 IOSC PULSEOUT2
1.0 V
+ -
PULSEOUT3 PGND GND
ROSC
CS5305
TYPICAL PERFORMANCE CHARACTERISTICS
900 800 700 Frequency (kHz) 600 500 400 300 200 100 10 20 30 40 50 ROSC Value (k) 60 70 0 10 20 30 40 50 ROSC Value 60 70 80 VFB Bias Current (A) 20 25
15
10
5
Figure 4. Oscillator Frequency
Figure 5. VFB Bias Current vs. ROSC Value
40 39 38 ENABL = Low ICC (mA) 37 36 35 34 33 0 25 50 75 Temperature (C) 100 125 ENABL = Floating Gates Switching Threshold Voltage (V)
9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 0 25
Start Threshold
Stop Threshold
50 75 Temperature (C)
100
125
Figure 6. ICC vs. Temperature
Figure 7. UVLO Start and Stop Thresholds vs. Temperature
1.354 Oscillator Frequency (kHz) 410 DAC Output (V) 0 25 50 75 Temperature (C) 100 125 1.353 1.352 1.351 1.350 1.349 400 1.348
405
0
25
50 75 Temperature (C)
100
125
Figure 8. Oscillator Frequency vs. Temperature for ROSC = 32.4 kW
Figure 9. DAC Output for VID = 01111 (1.475 V)
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CS5305
TYPICAL PERFORMANCE CHARACTERISTICS
1.582 140 135 Phase Delay (degrees) 1.580 DAC Output (V) 130 125 120 115 GATE1 to GATE2 110 105 1.572 0 25 50 75 Temperature (C) 100 125 100 0 25 50 75 Temperature (C) 100 125 GATE2 to GATE3 GATE3 to GATE1
1.578
1.576
1.574
Figure 10. DAC Output for VID = 00110 (1.700 V)
Figure 11. GATE Phase Delay vs. Temperature
10
95
Minimum Pulse Width (ns)
Rise/Fall Times (ns)
Rise Time 8.0
90
85
80
6.0 Fall Time CLOAD = 100 pF 4.0 0 25 50 75 Temperature (C) 100 125
75
70
0
25
50 75 Temperature (C)
100
125
Figure 12. GATE Rise and Fall Time vs. Temperature
Figure 13. PWM Comparator Minimum Pulse Width vs. Temperature
160 Transient Response Time (ns) Start-Up Offset Voltage (mV) 0
700 650 600 550 500 450 400
140
120
100
80
25
50 75 Temperature (C)
100
125
0
25
50 75 Temperature (C)
100
125
Figure 14. PWM Transient Response Time vs. Temperature
Figure 15. Current Sense Amp Channel Start-Up Offset Voltage vs. Temperature
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TYPICAL PERFORMANCE CHARACTERISTICS
4.0 3.5 3.0 2.5 2.0 1.5 Current Sense Amp to PWM Comparator Gain 1.0 0 25 50 75 Temperature (C) 100 125 10.55 0 25 50 75 Temperature (C) 100 125 Current Sense Amp to VDRP Gain Current Sense Amp to OSCETGain VFB Bias Current (A) 10.90 V(VFB) = 1.9 V 10.85 10.80 10.75 10.70 10.65 10.60 V(VFB) = 1.0 V
Current Sense Gain (V/V)
Figure 16. Current Sense Amplifier Gain vs. Temperature
Figure 17. VFB Bias Current vs. Temperature for ROSC = 32.4 kW
8.0
VDRP to DAC Output Offset Voltage (mV) 0 25 50 75 Temperature (C) 100 125
8.5 VDRP Source Current (mA)
1.6
1.4
7.5
1.2
7.0
6.5
1.0
6.0
0.8
0
25
50 75 Temperature (C)
100
125
Figure 18. VDRP Source Current vs. Temperature
Figure 19. VDRP to DAC Output Offset Voltage vs. Temperature
4.5 SHARE Fault Output Voltage IOUT Output Current (mA) SHARE Bus Voltages (V) 4.0 3.5 3.0 2.5 SHARE OK Threshold 2.0 SHARE Full Load Accuracy 1.5 0 25 50 75 Temperature (C) 100 125
16.0 15.5 15.0 14.5 14.0 13.5 13.0
SHARE Fault Threshold SHARE Max Output Voltage
0
25
50 75 Temperature (C)
100
125
Figure 20. SHARE Bus Voltages vs. Temperature
Figure 21. IOUT Output Current vs. Temperature
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TYPICAL PERFORMANCE CHARACTERISTICS
IOUT to SCOMP Transconductance (A/V) 0 25 50 75 Temperature (C) 100 125 45 SHARE Offset Voltage (mV) 44 43 42 41 40 39 38 45 40 35 30 25 20 15
0
25
50 75 Temperature (C)
100
125
Figure 22. SHARE Offset Voltage vs. Temperature
Figure 23. IOUT to SCOMP Transconductance vs. Temperature
Power Good Upper Threshold Voltage (V)
Percentage Change Over Nominal (%)
0.06 0.04 0.02 0 -0.02 VID = 00000 -0.04 -0.06 VID = 11110
2.015 2.010 2.005 2.000 1.995 1.990 1.985 1.980 1.975 0 25 50 75 Temperature (C) 100 125
VID = 01110
0
25
50 75 Temperature (C)
100
125
Figure 24. Power Good Lower Threshold Voltage vs. Temperature
Figure 25. Power Good Upper Threshold Voltage vs. Temperature
235
Power Good Delay (s)
230
225
220
215
210
0
25
50 75 Temperature (C)
100
125
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APPLICATIONS INFORMATION
THEORY OF OPERATION Fixed Frequency Multi-phase Control
Multi-phase CPU controllers include the necessary control circuitry to implement several buck converters in parallel. These converters are configured to turn on at different times. This allows much higher output current than could be provided by a single converter. The apparent ripple frequency is increased and so output current can ramp up or down faster than a single converter with the same value of output inductor. Heat is also spread among multiple components. The CS5305 uses a fixed frequency, Enhanced V2 architecture. Each phase is delayed by approximately 120 from the previous phase. The GATE output for each channel changes to a logic high at the beginning of its oscillator cycle. Inductor current ramps up until the combination of the current sense signal and the output ripple trip the PWM comparator, at which time the GATE output changes to a logic low. Once low, the GATE output remains low until the next oscillator cycle begins, and the control loop will not respond until that time. The Enhanced V2 control loop will respond to line and load transients while the GATE output is high. Enhanced V2 control will respond within the off time of the converter.
SWITCH NODE
increases, the voltage at the positive input to the PWM comparator rises and terminates the PWM cycle. If the inductor starts the next cycle with higher current, the PWM cycle terminates earlier, thus providing negative feedback. A CSx input is provided for each channel, but the CSREF, VFB and COMP inputs are common to all phases. Current sharing between phases is accomplished by referencing all phases to the same error amplifier. Any phase with a larger current signal will turn off earlier than the channels with a lower current signal. Including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. In the absence of any load current, the COMP pin voltage will be equal to the sum of the output voltage, the offset voltage and half of the steady-state ramp voltage. (At no load, the output ripple current's positive and negative contributions are equal, and the DC averaged voltage is equal to half the ripple voltage.) If the COMP pin is held steady and the inductor current is forced to change, the output voltage will also change. In a closed-loop situation, changing the inductor current will force the COMP voltage to change so the output voltage can remain the same. The change in COMP voltage depends on the scaling of the current feedback signal, and can be defined as:
DVCOMP + (ESRL)(Current Sense Gain)(DIPHASE)
L
RCSx CSx +
CS AMP
Since the current sense gain for this loop is unity, this equation reduces to:
DVCOMP + (ESRL)(DIPHASE)
ESRL
CCSx CSREF VFB
-
OFFSET
and so the single-phase power stage output impedance is:
+
PWM COMP
DVCOMP DIPHASE + ESRL
VOUT
- -
ERROR AMP
The CS5305 has three phases, so the total power stage output impedance is then ESRL/3.
Lossless Inductive Current Sensing
+ COMP CCOMP
Figure 27.
The Enhanced V2 architecture measures and adjusts current in each phase. An additional input (CSx pin) provides current information for each output phase to the control loop as shown in Figure 27. Inductor current is measured across capacitor Ccsx. The voltage across this capacitor is equal to the product of the output current and the inductor ESR if these components are chosen such that (Ccsx)(Rcsx) = (L)/ESRL. This signal is buffered by the current sense amplifier (unity gain in the CS5305) and summed with an offset voltage before it is presented as input to non-inverting input of the PWM comparator. Inductor current provides the PWM ramp. As inductor current
Current can be sensed across the inductor as shown in Figure 27. The output inductor is designated L and the inductor's equivalent series resistance is designated ESRL. In the ideal case, the values of Rcsx and Ccsx are chosen such that (L/ESRL) = (Rcsx)(Ccsx). If this criterion is met, the current sense signal will have the same shape as the inductor current, and the circuit can be analyzed as if a sense resistor with value equal to ESRL was placed in series with the inductor. However, these components also determine the ramp signal that is used to prevent pulse skipping and duty cycle jitter. Choosing (Rcsx)(Ccsx) < (L/ESRL) will result in the AC portion of the current sense signal being scaled more than the DC portion. This results in a larger ramp signal, but the current signal will overshoot during transients. This will affect transient response, adaptive voltage positioning and current limit. The COMP pin voltage will overshoot along with the current signal in order to maintain the output voltage. The COMP voltage will
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eventually find the correct level for regulation, but the error will decay with the time constant (Rcsx)(Ccsx). The VDRP voltage will also overshoot and response will be slowed, since the current signal is a component of that voltage. The single phase current limit will trip earlier since the current signal appears larger than it should be, and the module current limit will have a lower threshold for fast transients than it will for slow transients. Additional external components in the droop circuit and in the error amp compensation will correct this condition. Details are provided in the data sheet section on choosing external components.
Adaptive Voltage Positioning
becomes active. When the load decreases, the overshoot causes the output voltage to exceed the upper limit. The fast adaptive positioning waveform shows how AVP can reduce transient voltage requirements by about one half compared to a "normal" converter.
Adaptive voltage positioning is a technique used to reduce peak-to-peak output deviations during output current transients. The output voltage is set higher than nominal at light loads to reduce output voltage sag when load current is suddenly increased. Similarly, output voltage is set lower than nominal at heavy loads to reduce overshoot when load current suddenly decreases. The CS5305 implements adaptive voltage positioning by placing a resistor divider between VDRP and VOUT. The center tap of the divider connects to VFB. These resistors, along with two or three other external components, implement a lossless droop voltage function. Past implementations of adaptive voltage positioning used a droop resistor. This resistor was placed in series between the regulation point of the output voltage and the load. Increasing the current to the load caused the voltage at the load to droop below the regulation point. The amount of droop was equal to the change in current multiplied by the droop resistor value. This method was acceptable for low values of output current, where the droop resistor provided a minimal change in voltage without dissipating a great deal of power. Higher output current levels and tighter droop voltage requirements in today's microprocessors have rendered this droop resistor technique unusable. The lossless technique solves these problems. The AVP function addresses DC and slow transient output voltage positioning. Response during the first few hundreds of nanoseconds of a transient are addressed primarily by the power stage output impedance, and the ESR and ESL of the output filter. The ramp size and the error amplifier compensation control the transition between these two regions. If ramp size is too large or the error amp is too slow, there will be a long transition to the final voltage after a transient. This will be most apparent if the output capacitance is low. Figure 28 shows how adaptive positioning works. The waveform labeled "normal" shows output voltage for a converter without adaptive voltage positioning. The voltage sags when current steps up, returns to its nominal value and then overshoots when the current load is decreased. Using a slow adaptive positioning circuit can actually worsen performance. The slow adaptive positioning waveform above shows the output voltage sag, but the voltage recovers to its initial value before the adaptive positioning circuit
Normal Fast Adaptive Positioning Slow Adaptive Positioning Limits
Figure 28. Adaptive Positioning Current Limit
The CS5305 features two separate current limit circuits. First, the per-phase current limit terminates topside switch conduction in a phase if the voltage between any CSx pin and CSREF exceeds a typical value of 90 mV. This provides fast peak current protection for individual phases. In addition, the output current signals for all three phases are summed and filtered to provide an average module current signal. This signal is compared to a voltage that is user-programmable. If this voltage is exceeded, the fault latch is set and the COMP capacitor is discharged by a 5 A current sink until the COMP voltage falls below 0.2 V. The soft-start cycle begins when this threshold is reached, and the converter will operate in hiccup-mode until the overcurrent condition is cleared.
Error Amplifier
The CS5305 uses the Enhanced V2 control method to offer the fastest and most accurate regulation available. One of the features of this control method is ease of error amplifier compensation. A single capacitor placed from the COMP pin to ground is sufficient to adequately stabilize the error amplifier.
200 100
120
VDB(VY2) in db(Volts)
160 Phase(VY2) in Deg
60
20 1 2 -20
80
40 2
-60 1 100 1.0 k 10 k Frequency in Hz 100 k
Figure 29. Error Amplifier Frequency Response with No Compensation
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Enable
80 170
40 +Result of VDB(VY1) Phase(VY1) in Deg
150
The CS5305 has a dedicated enable pin, in accordance with the latest VRM specifications. This pin is internally pulled up to a 3.3 V rail through a blocking diode and a 50 k resistor. The blocking diode allows external pull up to a bias voltage greater than 3.3 V but below 13 V.
2
0
130
Fault Protection Logic
-40
110
-80 2
90 1 10 100 1.0 k Frequency in Hz 10 k
1
Figure 30. Error Amplifier Frequency Response with 0.1 mF Capacitor Soft Start/Hiccup Mode
The CS5305 is equipped with sophisticated fault-detection and protection circuitry to ensure proper operation in a paralleled VRM environment. In such an environment, any one of several distinct failures could not only destroy the VRM that sees the fault, but also those VRMs that are connected in parallel with the faulted VRM. Table 1 describes the fault logic circuitry, shown below in Figure 31.
UVLO ENABLE VID FAULT COMP DISCHG'D? S LOCAL FAULT LATCH FAULT
At initial power-up, the COMP voltage is zero. The total COMP capacitance will begin to charge with a typical current of 30 A. (There may be more than one capacitor connected between COMP and ground depending on the adaptive voltage positioning compensation.) All GATE outputs are held low until the COMP voltage reaches 0.6 V. Once this threshold is reached, the GATE outputs are released to operate normally. In hiccup-mode, this will result in GATE pulses being generated until the module overcurrent condition reoccurs, and the discharge/Soft Start cycle begins anew.
Undervoltage Lockout
R
OVC
S SHARE FAULT LATCH
R
SHARE FAULT
SHARE BUS HIGH?
The CS5305 includes an under-voltage lockout circuit. This circuit disables the output drivers until VCC applied to the IC reaches a typical value of 9 V. The GATE outputs are disabled when VCC drops below 8 V typical.
Table 1. Description of Fault Logic
Fault Modes Under Voltage Lockout VID = 11111 Enable Low Module Over Current (set by OCSET) Phase Over Current (0.33 V limit) External Share Fault (SHARE > 3.8 V) PWRGDS out of window range Stop Switching yes yes yes yes terminate pulse yes no DRVON Level low low low low high low high PWRGD Level low via Power Good window comparator low via Power Good window comparator low low via Power Good window comparator n/a low via Power Good window comparator low SHARE n/a n/a n/a > 3.8 V n/a n/a n/a
Figure 31. Fault Logic Circuitry
Controller Off no no no no no no no
COMP Pin Characteristics -5.0 A -5.0 A -5.0 A -5.0 A not affected -2.5 mA not affected
Reset Method Comp < 0.2 V Comp < 0.2 V Comp < 0.2 V Comp < 0.2 V not affected remove external 3.8 V from SHARE not affected
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Gate Outputs
The CS5305 is designed to operate with external gate drivers. Accordingly, the gate outputs are capable of driving a 100 pF load with typical rise and fall time of 15 ns.
DRVON
sees such a code, the GATE pins stop switching and go low. The DRVON signal also goes low, which turns off all FETs on the module if the FET driver has an enable input. This condition is described in Table 1.
PWRGD
Digital to Analog Converter (DAC)
The output voltage of the CS5305 module is set by means of a 5-bit, 1% DAC. The DAC pins are internally pulled up to a 3.3 V rail through a blocking diode and a set of 50 k resistors. The blocking diode allows external pull up to a bias voltage greater than 3.3 V and less than 13 V. The output of the DAC is described in the Electrical Characteristics section of the datasheet. These outputs are consistent with the latest VRM specifications. The DAC produces an output voltage 125 mV lower than the VID code would indicate in order to produce an accurate PWRGD output. The relationship between the VID code and the DAC code is described by Figure 32 shown below. The shaded area shows the acceptable range of output voltages. In order to produce a workable VRM using the CS5305, the designer is expected to use AVP as described earlier to position the output voltage above the DAC output, resulting in an output voltage somewhere in the middle of the acceptable range.
VOUT
LOW
-2.6% +2.6%
0.975 x (VID - 125 mV)
Figure 33. PWRGD Assertion Window
MIN VOUT
The latest VRM specifications require a module to turn its output off in the event of a 11111 VID code. When the DAC
EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE
MAX VOUT
VID code
In addition, certain fault modes must cause PWRGD to go low to signal the system board that a VRM fault has occurred. In that sense, the PWRGD signal operates as a "VRM BAD" signal. These fault modes, as shown in Table 1 above, are ENABL low and CSx out of window. When the ENABL pin is pulled low, PWRGD is pulled low to indicate that the VRM is off. DRVON is pulled low to turn both FETs off if the FET driver has an enable input. The logic circuitry inside the chip sets PWRGD low only after a delay period has been passed. A "power bad" event does not cause PWRGD to go low unless it is sustained through the delay time, typically 200 s. If the anomaly disappears before the end of the delay, the PWRGD output will never be set low. In order to use the PWRGD pin as specified, the user is advised to connect external resistors as necessary to limit the current into this pin to 4 mA or less.
Share Bus
125 mV DAC output
Figure 32. VRM 9.0 Output Voltage Accuracy Requirements
VRM 9.x specifications require that a single-wire share bus be provided from each module. This bus allows output current information to be communicated between modules such that the total load current is shared equally by each module. The CS5305 employs a proprietary share algorithm called direct duty cycle control. A block diagram is provided in Figure 34.
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EEEE EEEE CCCC CCCC CCCC
-5.0% +5.0%
EEE EEE CCC CCC CCC
When the CS5305 is used with DRVON-compatible gate drivers, the ability of the system to survive a fault in a paralleled environment is greatly increased. The DRVON signal tells the gate drivers to shut off both FETs while entering a fault condition. This action takes the faulted VRM "out of the picture," allowing the system to operate until the bad module can be replaced.
According to the latest VRM specifications, the PWRGD signal is to be asserted when the output voltage is within a window defined by the VID code, as shown in Figure 33.
PWRGD PWRGD low HIGH PWRGD high PWRGD low
VOUT
1.975 V
CS5305
VOUT + VOFFSET + 1x CURRENT SENSE INPUT 3.7x CURRENT SENSE INPUT
+ + -
SHARE ADJUST AMP +
3.3 V
SHARE CURRENT SENSE AMP
- SHARE BUS AMP -+ 30 mV -
+ RESET - PWM COMPARATOR PWM LATCH SET FROM OSCILLATOR GATE DRIVER GATEx
IFB
IOUT
SHARE
SCOMP
COMP
Figure 34.
Direct duty cycle control utilizes a master-slave approach to current sharing. At any given current load, one module will have a higher share bus voltage than the other modules. This module acts as the master. It conveys output current information to the other modules via the share bus. This information is buffered and provided to the PWM comparators, thus directly controlling duty cycle for the slave modules. The share current sense amplifier allows the user to customize the share bus transconductance. Current sense information is provided to the non-inverting input from the 3.7x current sense amplifier from each phase. This provides a representation of the total module current. An external resistor divider between IOUT and ground, center-tapped at IFB programs the share bus voltage for a particular current level. The share bus amplifier serves as a buffer and places the IOUT voltage on the SHARE pin. Note there is a diode in the schematic between the share bus amplifier and the SHARE pin. This is an "ideal" diode, and indicates that the share bus amplifier does not have current sink capability. This allows the share bus to be driven by the module with the highest share bus voltage. A 30 mV offset voltage provides noise immunity to ensure that any given module does not cycle between master and slave in a random fashion. It also guarantees that the master module is not driving duty cycle from the share bus. For the master module, the IOUT and SHARE voltages will be equal. In this case, the 30 mV offset holds the share adjust amplifier inactive, and the PWM channel is controlled in the normal manner. The offset voltage results in a current error between the master and slave modules, but this error is small compared to the current share tolerance found in the VRM 9.x specifications. The share adjust amplifier takes the share bus voltage and directly drives the PWM comparators of all slave modules as previously described. The SCOMP pin provides a connection point for a compensation capacitor for the share adjust amplifier.
CHOOSING EXTERNAL COMPONENTS FOR THE CS5305
ROCSET and ROSC
The ROSC lead of the CS5305 provides a fixed 1 V reference to the user. A resistive divider is connected from ROSC to ground as shown in Figure 35. The center tap of the divider is connected to the OCSET lead. The total resistance from the ROSC lead to ground programs the oscillator frequency for the converter according to the chart in Figure 36. The resistive divider also sets a voltage on the OCSET lead. This voltage programs the module overcurrent trip point. The module overcurrent comparator, or OC Comparator, uses the OCSET lead voltage as the reference against which the module output current signal is compared. The output current of each phase is given as (VCSx - VCSREF) divided by the equivalent series resistance of the inductor. The voltage information (VCSx - VCSREF) is gained up by a factor of 3.7 and summed for all three phases at the non-inverting input of the OC Comparator. The fault latch is set if the module overcurrent limit is exceeded. This results in "hiccup-mode" operation until the overcurrent condition is cleared.
ROSC R1 OCSET ROCSET
ROSC = R1 + ROCSET
Figure 35.
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900 800 700 FOSC (kHz) 600 500 400 300 200 100 10 20 30 40 50 R1 + ROSCSET (k) 60 70 CSx CCSREF Switch Node x RCSx L1 CCSx RCSREF = RCSx/3 CSREF VOUT
for the CS1, CS2 and CS3 leads, but the value of resistance should be one third that of RCSx:
RCSREF + RCSx 3
This change is necessary to compensate for the difference in bias current between the CSREF lead and each CSx lead. The schematic in Figure 37 shows the connection of these components.
Figure 36. FOSC vs. R1 + ROCSET
Additionally, the total value of resistance between ROSC and ground also programs the VFB pin bias current. VFB bias current is equal to 0.333 V divided by the total resistance from ROSC to ground. This current is used to generate the droop function in the adaptive voltage positioning circuitry and is discussed further in that section.
Current Sense Components
Figure 37. Share Bus Components
Current sense components are chosen for two reasons. First, the value of RCSx and CCSx should be chosen to meet the criterion:
(RCSx)(CCSx) w (L) (ESRL)
where L is the inductor value and ESRL is the inductor equivalent series resistance. Meeting this criterion will ensure that the module overcurrent limit is not exceeded during current transients. Second, RCSx and CCSx should be chosen to add a small amount of ramp to the system. This will provide stable, jitter-free operation. The amount of ramp voltage required depends on several factors: supply voltage, output voltage (DAC code), switching frequency and board layout all affect the amount of artificial ramp required to some degree. The power supply designer should be aware that choosing the value of artificial ramp is a trade-off. As artificial ramp amplitude increases, the system becomes less prone to duty cycle jitter, but transient response will suffer. Adding 20 mV of artificial ramp is a good compromise and can be used to start design. The current sense ramp is generated from the square wave obtained at the switching node of each phase by using an RC filter. The RC filter components for the CSx leads should be chosen to satisfy the following formula:
RCSx CCSx v (VOUT) 1 * VOUT VCC (fOSC)(VRAMP)
Five external components are required to implement the module-to-module current share function. These components set the current sense load line, provide the share bus pull-down and compensate the share adjust amplifier. The share current sense amplifier monitors the total module current and provides a DC voltage output proportional to that current. The share sense amplifier gain is programmable and allows the user to set the share bus transconductance. It is important that all modules in a system have a share current load line that approximates that of all the other modules to ensure accurate module-to-module current sharing. Let us arbitrarily set the share bus maximum voltage for full load at 2 V. If a module is designed to provide 81 A at full load, the module share transconductance should be 81 A/2 V or 40.5 A/V. Two resistors and a capacitor set the share current sense amplifier gain. The resistors set the DC gain while the capacitor provides a zero to minimize errors due to noise. The total module current is measured as described in the section dealing with the OCSET current limit function. That is, each phase within a module generates a voltage between the CSx and CSREF leads that is proportional to the current flow in the output inductor and the inductor's ESR:
VCSx * VCSREF + (IL)(ESRL)
This signal is amplified by a factor of 3.7 for each phase and then summed for all three phases. This signal is provided as input to the share current sense amplifier. If we assume that all three phases are sharing current equally within a single module, the input to the share current sense amplifier can be expressed as:
VIN(SENSE) + 11.1(VCSx * VCSREF) + 11.1(IL)(ESRL) + 3.7(IOUT)(ESRL)
Choose a convenient standard value for CCSx and solve for the value of RCSx. Each of the three output phases requires its own RC combination. An RC filter is also required for the CSREF connection. This filter may use the same value of capacitance identified
If we set IL equal to the maximum per phase current at full load, and if we know the value of ESR for our inductors, we
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can calculate the required share current sense amplifier gain as:
AV(SHARESENSE) + share maximimum voltage VIN(SENSE)
lead voltage to 3 V. The share bus of one module serves as master to all and drives the total resistance of all SHARE leads. Thus, the total impedance of all share resistors should be made greater than or equal to 3 k. That is,
3 kW w RSHARE N
As an example, let us again consider the case for a module providing full load current of 81 A. Each output phase is conducting 27 A. If we assume ESR = 1.5 m then input to the share current sense amplifier is (11.1)(27 A)(1.5 m) = 0.45 V. The required share current sense amplifier gain is then 2 V/0.45 V = 4.44.
VIN(SENSE) + - RIOUT IFB RIFB CIOUT IOUT
where N is the maximum number of modules that can be placed in parallel as defined by the designer. As an example, if ten is the maximum number of modules that may be paralleled, then the minimum value of RSHARE should be 30 k. The share resistor should also not be made too large, since this is the only pull-down on the SHARE lead. Transient response of the share bus is limited by the RC time constant of the share resistance and any parasitic capacitance found on the SHARE line between modules.
Droop Components
Figure 38.
From the schematic in Figure 38, we derive the DC gain as:
AV(SHARESENSE) + 4.44 + RIOUT RIFB ) 1
This specifies that RIOUT should be 3.44 times greater than RIFB. Another important consideration is the type of resistor selected for RIFB. The thermal performance of RIFB must match that of whatever sense element is being used to monitor module current. Inductive sensing has been shown to be reasonably accurate, but copper's thermal coefficient of resistivity is approximately +4000 parts per million per C (0.4% per C). In order to maintain accurate control of the share bus over temperature, RIFB must have a similar thermal coefficient. This requires a positive temperature coefficient element such as the KOA-Speer LT73. If a standard sense resistor is used in series between the inductor and the load, there is no need to use special resistors for sensing, but efficiency will suffer due to power dissipation in the sense resistor. As regards the value of CIOUT, it should be noted that the complete transfer function for the share current sense amplifier in Figure 38 is:
AV(SHARESENSE) + RIOUT )1 RIFB(1 ) sCIOUT RIOUT)
The CS5305 offers adaptive voltage positioning. This feature allows the output voltage to be set at different levels according to the amount of current being provided by the module. The output voltage is somewhat higher than nominal under no load or light load conditions and somewhat lower than nominal under heavy load conditions. Both set points must fall within the Power Good window. The adaptive positioning allows for overshoot and undershoot conditions that occur during load current transients and results in a reduction in the peak-to-peak VOUT voltage excursion during load current transients. Three components are required to implement DC adaptive voltage positioning. Resistor RFB is connected between the module VOUT(SENSE)+ lead and the VFB lead. Resistor RDRP is connected between the VDRP lead and VFB lead. Resistor RVSENSE is connected between the VOUT(SENSE)+ lead and the module VOUT lead. These connections are shown in Figure 39.
VDRP RDRP VFB RFB
VOUT(SENSE)+ RVSENSE VOUT
CIOUT causes the gain for high frequency noise to decrease, thus quieting the share bus. The share resistor provides a passive pull-down on the SHARE lead. This allows the share bus voltage to be pulled all the way down to ground. The share resistor is selected to satisfy a number of criteria. First, the resistor cannot be made too small. The SHARE lead source current is guaranteed to be above 1 mA and must be capable of driving the SHARE
Figure 39.
The first step in choosing these components is to select the appropriate no-load and full-load output voltage set points for the particular DAC code being used. Additionally, the values of ROSC and ROCSET should be known, as should ESR of the output inductors and the full-load output current.
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CS5305
V(DAC) + OUTPUT STAGE - RDRP VDRP VFB I(VFB) RFB VOUT
Figure 40.
As was previously noted, the total value of resistance between the ROSC pin and ground sets the VFB lead bias current according to:
I(VFB) + 0.333 V (ROSC ) ROCSET)
the test tool so a function generator can drive it. Using lower frequency (approximately 100 Hz) and lower duty cycle (10%) allow the designer to better observe the true settling behavior of the VRM module. It may be necessary to add some filtering components to the droop voltage divider. These components cause the AC and DC gain from the current sense circuitry to match and allow the user to tailor the droop output voltage performance. There are two methods for tuning droop performance. The first is illustrated in Figure 41. In this case, capacitors CDRP and CFB are placed in parallel with RDRP and RFB. A third capacitor CDRCMP is connected between the COMP and VDRP leads. The first two capacitors correct any gain errors introduced in the selection of current sense components Rcsx and Ccsx. Values for these components are defined as:
CFB + L ((RFB)(ESRL))
Referring to Figure 40, the VDRP lead voltage is equal to the DAC voltage plus the current sense information. Under no load conditions, the VDRP and VFB pin voltages are equal, and the entire VFB bias current flows between VOUT(SENSE)+ and VFB through RFB. Because the VFB bias current sinks into VFB, the output voltage is forced to be higher than the DAC voltage, and so the value of RFB can be calculated as:
RFB + (VOUT no load set point * VDAC) I(VFB)
and
CDRP + ((CCSx)(RCSx)) RDRP
With RFB chosen, we can now select the value of RDRP. If we again refer to Figure 40, we can use Kirchoff's Current Law at the VFB node to find that the value of RDRP is defined as:
RDRP + (full load current)(3.7)(ESRL)(RFB) (RFB)(I(VFB)) ) V(DAC) * VOUT full load set point
The capacitor between VDRP and COMP allows the user to fine-tune the transition between "fast" AVP and the slower positioning set by resistors RDRP and RFB. This capacitor may or may not be required and is empirically chosen based on the fine-tuning procedure described below. A value of 1 nF is recommended as an initial value.
VDRP CDRP RDRP VFB CFB RFB
RVSENSE is used to ensure that a connection between VOUT and VOUT(SENSE) always exists. This ensures that the module will operate correctly in the event that the VOUT(SENSE) connection is broken. The module-to-load interface and the number of modules placed in parallel determine the value of RVSENSE. The CS5305 is specified to operate correctly with up to 55 mV dropped across the module connector. It is assumed that the maximum current allowed to flow in this connection to the load is 1 mA.
RVSENSE + 55 mV (1 mA N)
VOUT(SENSE)+ CDRCMP RVSENSE VOUT
COMP
Figure 41.
where: N = the number of modules to be paralleled. If four modules are to be paralleled, each contributes a maximum of 250 A to this connection, and so RVSENSE = 55 mV/250 A = 220 . This component is placed to ensure the VRM module will regulate correctly if the module VOUT(SENSE)+ connection to the load is opened. The transient droop performance should be checked next. Performance should be verified using the transient test tool typically provided in a microprocessor development kit. True transient performance can be masked even at test frequencies as low as 2 kHz. It should be possible to modify
Set up the circuit to be tested with a DVM and oscilloscope to the output. Have the scope set to DC input and set its offset so a resolution of at least 100 mV/div is used and the output is visible on the screen. Using a DVM, measure the output voltage with no load. If this value differs from the expected value, adjust RFB until the nominal value is reached. Once this is set, mark this DC level on the scope with a cursor. Next, measure the output voltage with full DC load. If this value deviates from the expected value, adjust RDRP until the nominal value is reached. Once this is set, mark this DC level on the scope with another cursor.
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CS5305
No Load Cursor Marker
Full Load Cursor Marker
Trace 1: Optimal Trace 2: CFB too large Trace 3: CFB too small Trace 4: CDRCMP too large, CCOMP too small Trace 5: CDRCMP too small, CCOMP too large
Figure 42.
Using the transient test tool, set up a current load step from low current (1 A) to maximum load at the slew rate being designed for. Set the current step at about 100 Hz with a duty cycle of 10%. Converter response should be similar to that shown in Figure 42. Next, determine if there is a "bump" (trace 4 or trace 5) in the output. Adjust CCOMP and CDRCMP to flatten out this bump. If the "bump" is negative (trace 5), make CDRCMP slightly larger and CCOMP slightly smaller. If you see a positive "bump" (trace 4), make CDRCMP slightly smaller and CCOMP slightly larger. If performance is better without CDRCMP, just make C1 larger. Once the bump is removed, look to see if the "pulse step" magnitude is larger or smaller than the DC level (trace 2 or trace 3). Make CFB slightly larger if the AC gain (trace 3) is too large or slightly smaller if the AC gain (trace 2) is too small. Once the output response resembles the "optimal" trace (trace 1), the controller has been optimized for the design from a static and dynamic response. If the output appears to be jittering slightly prior to optimizing transient response, make the previous adjustments first, since they may solve the problem. If the problem persists, decreasing the value of Rcsx across the inductor will increase ramp amplitude, and jitter performance should improve with increased ramp. The second method uses a capacitor to "square up" the COMP waveform and a series resistor and capacitor to tune the VDRP waveform. These components are chosen empirically based on observations of COMP and VDRP performance. First, set the test tool for a load current transient from no load (1 A) to full load and observe the COMP waveform.
The COMP waveform should ideally be flat, or at worst decrease slightly during a current increase transient. The principle at work here is that the increase in current sense information will generate a voltage that should exactly cancel the droop voltage, and thus the COMP capacitor voltage should not change. In reality, it is unlikely that every manufactured module can be built to perfectly compensate the droop voltage, and so the COMP voltage should exhibit a small amplitude square wave during transient conditions. If the COMP voltage is decreasing gradually, the current sense information is too small to fully compensate for the droop voltage, and the designer should add a capacitor between VOUT and COMP. This capacitor is chosen empirically, with 1 nF a good starting point. This capacitor will pull the COMP pin down initially and "square up" the COMP waveform as shown in Figure 43.
Current Transient COMP Ideal Waveform COMP Uncorrected Waveform VOUT Uncorrected Waveform COMP Corrected Waveform VOUT Corrected Waveform
Figure 43.
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CS5305
In a similar manner, if the current information is too large, the COMP voltage will rise to compensate. Again, a square wave is preferable to a slow change in the COMP voltage, and placing a capacitor between VDRP and COMP will "square up" the COMP waveform as shown in Figure 44. VFB up so COMP voltage decreases results in increasing output duty cycle. The series RC filter is now located in parallel with RDRP.
Current Step Current Transient VDRP COMP Ideal Waveform COMP Uncorrected Waveform VOUT Uncorrected Waveform COMP Corrected Waveform VOUT Corrected Waveform (RCSx)(CCSx) > L/ESRL
Figure 46.
These components are chosen empirically. The fastest way to optimize the design is to start with a 1 nF capacitor and a 500 k potentiometer and "dial in" performance.
Error Amplifier Compensation
Figure 44.
Once the COMP waveform has been squared up, it is necessary to check the VDRP waveform. The VDRP waveform is dependent on the choice of ramp components. If these components have been chosen such that (RCSx)(CCSx) = L / ESRL, the VDRP waveform should be a square wave that matches the current step. At this point, the VOUT waveform should also be a square wave and transient performance should be optimized. If (RCSx)(CCSx) < L / ESRL, the VDRP waveform will be faster than current step. The VDRP voltage will exhibit a fast rise followed by an exponential droop down to a DC level, as shown in Figure 45. This waveform has the effect of telling the system that transient current signals are larger than the true current. Response will be slowed, and VOUT will overshoot until the error amplifier "catches up". In this case, it is desirable to push the VFB pin down, so that COMP voltage is forced up and duty cycle is reduced slightly. This is done by placing a series RC filter across resistor RFB.
Error amplifier compensation is very simple using the enhanced V2 control architecture. A single 0.1 F capacitor from the COMP lead to ground is usually sufficient. As an alternative, a resistor and capacitor in series between COMP and ground may improve output voltage positioning during current transients. The resistance will speed up the effective slew rate of the error amplifier output. The COMP capacitor also provides soft start and hiccup-mode timing. At start-up, the COMP capacitance must charge from ground through a typical channel start-up offset of 0.6 V before the GATE outputs are allowed to begin switching. The COMP capacitance includes both the COMP capacitor and any droop compensation capacitance that may be connected to the COMP pin. The typical soft start time can then be approximated as:
TSOFT-START(ms) + 20 CCOMP(TOTAL)(mF)
Current Step
VDRP (RCSx)(CCSx) < L/ESRL
Figure 45.
If (RCSx)(CCSx) > L / ESRL, the VDRP waveform will be slower than the current step. VDRP will exhibit an initial spike, but the voltage will then exponentially rise toward its correct DC level, as shown in Figure 46. This waveform effectively tells the system that the current signal is smaller than the true current, and response will be faster than optimal. VOUT will then undershoot. In this case, forcing
Hiccup timing has a similar equation. During hiccup-mode, the COMP voltage traverses between the fault reset threshold (approximately 0.2 V) and the channel start-up offset voltage. When the fault circuitry becomes active, the COMP capacitor is discharged with a 5 A current until the fault reset threshold is reached. The time this initial discharge takes is variable depending on the COMP voltage when the fault occurred. Once the reset threshold is reached, the COMP capacitor is charged with the 30 A current until the start-up offset voltage is reached. The GATE outputs will begin to pulse, quickly ramping the inductor current. The fault circuitry can then re-detect the fault condition some number of GATE pulses later if it is still present. Thus, the period of the fault hiccup mode is approximately defined as:
THICCUP(ms) + 93.3 CCOMP(TOTAL)(mF)
Period is only approximately defined since the number of GATE pulses between restart and redetection of a fault condition is unpredictable.
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CS5305
Inductors
There are many factors to consider when choosing the output inductors. Maximum load current, core and winding losses, ripple current, short circuit current, saturation characteristics, component height and cost are all variables that the designer should consider. However, the most important consideration in designing for the VRM 9.x specifications may be the effect inductor value has on transient response. The amount of overshoot or undershoot exhibited during a current transient is defined as the product of the current step and the output filter capacitor ESR. To some degree, adaptive voltage positioning is used to "pre-position" the output voltage so the voltage step during a current transient will not cause the output voltage to exceed the Power Good window. However, adaptive positioning will not completely eliminate the overshoot or undershoot conditions, and choosing the inductor value appropriately can minimize the amount of energy that must be transferred from the inductor to the capacitor or vice-versa. In the subsequent paragraphs, we will determine the minimum value of inductance required for our system and consider the trade-off of ripple current vs. transient response. In order to choose the minimum value of inductance, input voltage, output voltage and output current must be known. Most computer applications use reasonably well regulated bulk power supplies so that, while the equations below specify VIN(MAX) or VIN(MIN), it is possible to use the nominal value of VIN in these calculations with little error. Current in the inductor while operating in the continuous current mode is defined as the load current plus ripple current.
IL + ILOAD ) IRIPPLE
Since the maximum output current must be less than the maximum switch current, the minimum inductance required for a single phase can be determined.
(VIN(MIN) * VOUT)VOUT L(MIN) + (fOSC)(ISWITCH(MAX))(VIN(MIN))
This equation identifies the value of inductor that will provide the full rated switch current as inductor ripple current, and will usually result in inefficient system operation. The system will sink current away from the load during some portion of the duty cycle unless load current is greater than half of the rated switch current. Some value larger than the minimum inductance must be used to ensure the converter does not sink current. Choosing larger values of inductor will reduce the ripple current, and inductor value can be designed to accommodate a particular value of ripple current by replacing ISWITCH(MAX) with a desired value of IRIPPLE:
(VIN(MIN) * VOUT)VOUT L(RIPPLE) + (fOSC)(IRIPPLE)(VIN(MIN))
However, reducing the ripple current will cause transient response times to increase. The response times for both increasing and decreasing current steps are shown below.
TRESPONSE(INCREASING) + (L)(DIOUT) (VIN * VOUT) (L)(DIOUT) (VOUT)
TRESPONSE(DECREASING) +
The ripple current waveform is triangular, and the current is a function of voltage across the inductor, switch FET on-time and the inductor value. FET on-time can be defined as the product of duty cycle and switch frequency, and duty cycle can be defined as a ratio of VOUT to VIN. Thus,
IRIPPLE + (VIN * VOUT)VOUT (fOSC)(L)(VIN)
Inductor value selection also depends on how much output ripple voltage the system can tolerate. Output ripple voltage is defined as the product of the output ripple current and the output filter capacitor ESR. However, since the CS5305 has three paralleled phases, the net effect is that the switching frequency as seen by the output capacitance is tripled relative to the CS5305 operating frequency. This is because each phase switches in sequence and the ripple currents in each phase are superimposed on the output capacitance. This is illustrated graphically in Figures 45 and 46. Thus, output ripple voltage can be calculated as:
VRIPPLE + ESRC IRIPPLE + ESRC VIN * VOUT VOUT 3 fOSC L VIN
Peak inductor current is defined as the load current plus half of the peak current. Peak current must be less than the maximum rated FET switch current, and must also be less than the inductor saturation current. Thus, the maximum output current for a single phase can be defined as:
IOUT(MAX) + ISWITCH(MAX) * VIN(MAX) * VOUT VOUT 2 fOSC L VIN(MAX)
It is also important to note that the maximum value of inductor ESR is limited by the single-phase pulse-by-pulse current limit. The specified minimum value for this parameter is 80 mV, so the maximum inductor ESR is:
ESRL(MAX)(in ohms) + (0.08 V) single phase current limit value in Amps
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CS5305
VCC Bypass Filtering
PHASE 1 SWITCH NODE PHASE 2 SWITCH NODE PHASE 3 SWITCH NODE
A small RC filter should be added between module VCC and the VCC input to the CS5305. A 10 resistor and a 0.1 F capacitor should be sufficient to ensure the controller IC does not operate erratically due to injected noise.
Module Input Filter Capacitors
SUPERIMPOSED PHASE INDUCTOR CURRENTS
The input filter capacitors for the VRM module provide a charge reservoir that minimizes supply voltage variations due to changes in current flowing through the switch FETs. These capacitors must be chosen primarily for ripple current rating.
LIN VIN IIN(AVE) CIN
CONTROL INPUT
PHASE 1 CURRENT PHASE 2 CURRENT PHASE 3 CURRENT OUTPUT RIPPLE CURRENT
LOUT VOUT COUT
Figure 47.
Finally, we should consider power dissipation in the output inductors. Power dissipation is proportional to the square of inductor current:
( ) PD + I 2 PHASE) ESRL
IRMS(CIN)
Figure 48.
The temperature rise of the inductor relative to the air surrounding it is defined as the product of power dissipation and thermal resistance to ambient:
DT(inductor) + (Ra)(PD)
Consider the schematic shown in Figure 48. The average current flowing in the input inductor LIN for any given output current is:
IIN(AVE) + (IOUT)(VOUT VIN) + (IOUT per phase)(n)(D)
Ra for an inductor designed to conduct 20 A to 30 A is approximately 45C/W. The inductor temperature is given as:
T(inductor) + DT(inductor) ) Tambient Output Filter Capacitors
Each microprocessor manufacturer specifies output filter capacitors for the motherboards. In addition, the designer may need to add some output capacitance on the VRM module. These added output capacitors would serve to reduce the noise floor and help ensure jitter-free operation. If needed, one or two ceramic capacitors should be sufficient. They should have a 4 WVDC rating. Large amounts of bulk capacitance placed on the VRM module are not useful, since the impedance of the VRM connector exists between the module and the load. Low equivalent series resistance is important since output ripple voltage and response to output current transients are largely dependent on this parasitic parameter.
where: D = duty cycle, n = number of phases. Input capacitor current is positive into the capacitor when the switch FETs are off, and negative out of the capacitor when the switch FETs are on. When the switches are off, IIN(AVE) flows into the capacitor. When the switches are on, capacitor current is equal to the per-phase output current minus IIN(AVE). If we ignore the small current variation due to the output ripple current, we can approximate the input capacitor current waveform as a square wave. We can then calculate the RMS input capacitor ripple current:
IRMS(CIN) + I2 IN(AVE) ) D n
IOUT per phase * IIN(AVE) 2 * I 2 IN(AVE)
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CS5305
The input capacitance must be designed to conduct the worst case input ripple current. This will require several capacitors in parallel. In addition to the worst case current, attention must be paid to the capacitor manufacturer's derating for operation over temperature. As an example, let us define the input capacitance for a 12 V to 1.7V conversion at 81 A, or 27 A per phase at an ambient temperature of 60C. A droop voltage of 90 mV to 1.61 V and efficiency of 80% is assumed. Average input current in the input filter inductor is:
IIN(AVE) + (27 A)(3 phases)(1.61 V 12 V) + 10.868 A 80%
Input capacitor RMS ripple current is then
IIN(RMS) + 10.8682 ) 1.61 V 3 12 V 27 A * 10.868 A 2 * 10.868 A2
parallel, the effective RDS(ON) is reduced, thus reducing the ohmic power loss. However, placing FETs in parallel increases the gate capacitance so that switching losses increase. As long as adding another parallel FET reduces the ohmic power loss more than the switching losses increase, there is some advantage to doing so. However, at some point the law of diminishing returns will take hold, and a marginal increase in efficiency may not be worth the board area required to add the extra FET. Additionally, as more FETs are used, the limited drive capability of the FET driver will have to charge a larger gate capacitance, resulting in increased gate voltage rise and fall times. This will affect the amount of time the FET operates in its ohmic region and will increase power dissipation. The following equations can be used to calculate power dissipation in the switch FETs. For ohmic power losses due to RDS(ON):
PON(TOP) + (RDS(ON)(TOP))(IRMS(TOP))2(n) (number of topside FETs per phase)
RDS(ON)(BOTTOM) IRMS(BOTTOM) 2 n) number of bottom-side FETs per phase
+ 13.347 A
If we consider a Sanyo SP series capacitor, the ripple current rating for a 16SPS100M capacitor is 2820 mA at 100 kHz and 45C. The derating factor is 0.85 for operation up to 65C, resulting in an effective ripple current rating of 2397 mA. We determine the number of input capacitors by dividing the ripple current by the per-capacitor current rating:
Number of capacitors + 13.347 A 2.397 A + 5.52
PON(BOTTOM) +
A total of at least 6 capacitors in parallel must be used to meet the input capacitor ripple current requirements.
Output Switch FETs
where: n = number of phases. Note that RDS(ON) increases with temperature. It is good practice to use the value of RDS(ON) at the FET's maximum junction temperature in the calculations shown above.
IRMS(TOP) + I 2 * (IPK)(IRIPPLE) ) D I 2 PK 3 RIPPLE (1 * D) 2 I RIPPLE 3
Output switch FETs must be chosen carefully, since their properties vary widely from manufacturer to manufacturer. The CS5305 system is designed assuming that a FET driver IC and n-channel FETs will be used. The FET characteristics of most concern are the gate charge/gate-source threshold voltage, gate capacitance, on-resistance, current rating and the thermal capability of the package. FET driver ICs have a limited drive capability. If the switch FET has a high gate charge, the amount of time the FET stays in its ohmic region during the turn-on and turn-off transitions is larger than that of a low gate charge FET, with the result that the high gate charge FET will consume more power. Similarly, a low on-resistance FET will dissipate less power than will a higher on-resistance FET at a given current. Thus, low gate charge and low RDS(ON) will result in higher module efficiency and will reduce heat being generated by the VRM module. It can be advantageous to use multiple switch FETs to reduce power consumption. By placing a number of FETs in
IRMS(BOTTOM) + I 2 * (IPKIRIPPLE) ) PK IRIPPLE +
(VIN * VOUT)(VOUT) (fOSC)(L)(VIN)
I I I IPEAK + ILOAD ) RIPPLE + OUT ) RIPPLE 2 3 2
where: D = Duty cycle. For switching power losses:
PD + nCV2(fOSC)
where: n = number of switch FETs (either top or bottom) per phase, C = FET gate capacitance, V = maximum gate drive voltage (usually VCC), fOSC = switching frequency.
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External FET Driver Layout Considerations
The CS5305 is designed such that an external FET driver IC is required. The GATE pin outputs are designed to drive a 100 pF load, and do not have sufficient drive capability to directly drive the gates of switch FETs. The GATE outputs have a typical output high voltage of 2.5 V, so the turn-on threshold of the FET driver should be approximately 2 V. The GATE outputs are also phased such that the FET driver IC should turn on the topside n-channel FET when the GATE output goes high. The bottom-side n-channel FET should be on when the GATE output is below the FET driver IC turn-on threshold. Additionally, the CS5305 provides a signal called DRVON that can be connected to the ENABLE pin of FET drivers that offer an enable feature. If the FET driver's ENABLE input is high, the FET driver output is determined by the GATE input, and the switch FETs are driven according to the conditions described above. If the FET driver's ENABLE input is low, all switch FETs are turned off and no current is conducted to the load. This DRVON signal is a logic output from the CS5305. DRVON goes high when all internal functions of the CS5305 are operating correctly and the IC is not in fault mode. A table of the DRVON logic may be found in the Theory of Operation section. Choosing a FET driver IC with an enable feature significantly improves system reliability, since a faulty module is essentially disconnected from the load.
SGND Resistor
The module-to-load interface and the number of modules placed in parallel determine the value of RSGND. The CS5305 is specified to operate correctly with up to 55 mV dropped across the module connector. It is assumed that the maximum current allowed to flow in this connection to the load is 1 mA.
RSGND + 55 mV (1 mA N)
Enhanced V2 performs best under dynamic load conditions if current ramp is kept small. However, this may lead to pulse-width jitter or pulse skipping, particularly as the ambient noise level at the control circuit increases. This is a complicated design trade-off that can not be mathematically characterized, and it is crucial to have a "quiet" layout. Following the design/layout guidelines below will provide the best system performance. Refer to Figure 50 for a layout example and to page 2 for the associated schematic. Numbers in parentheses refer to IC pin numbers. Component names refer to the reference designators for the application schematic. 1.Noise across the PWM comparator inputs needs to be low or pulse width jitter will occur. Referring to the block diagram, the CSREF pin (7) and the COMP pin (14) present external information to the PWM comparator. Any differential signal across these pins is expressed directly across the PWM comparator, which may cause pulse-width jitter or pulse skipping. The solution is to provide a dedicated Kelvin connection for sensing the VRM's VOUT-. The IC's GND pin (28) and COMP capacitance need a dedicated sense line to VOUT-, in effect making the IC and COMP capacitance VOUT-ground-referenced. This is desirable since the fast feedback path through CSREF is connected to VOUT+ and is therefore also VOUT-ground-referenced. Furthermore, a ground strip under the IC is desirable since the COMP pin is located at the opposite corner of the IC from the GND pin. This ground strip further reduces the ambient noise level of the CS5305 along with providing a good connection from COMP return to GND and VOUT-. Following this guideline will provide the most system improvement from a layout standpoint.
where: N = the number of VRM modules to be paralleled. If four modules are to be paralleled, each contributes a maximum of 250 A to this connection, and so,
RSGND + 55 mV 250 mA + 220 W
This component is placed to ensure the VRM module will regulate correctly if the module VOUT(SENSE)- connection to the load is opened.
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or
VOUT+ sense VOUT- sense
VOUT+ sense VOUT- sense
Figure 49.
2.Differential noise across the PWM comparator can be further reduced if the VOUT+ and VOUT- sense lines going to CSREF and GND are paralleled to minimize loop area. VOUT+ ripple information provided to the PWM comparator via the CSREF pin needs to be symmetric for all three phases or poor current sharing between phases will occur. This can be accomplished by placing the VOUT+ and VOUT- sense locations symmetrically with respect to the three output inductors. See Figure 49. 3.Frequency jitter could occur if the ROSC pin (2) and OCSET pin (1) components are not properly located. Most layouts will have two resistors in series from ROSC to GND. Keep these two components as close as possible to the IC and ensure a short ground connection to the IC GND. Provision for a small cap (1000 pF or less) from ROSC to GND can be placed although this is rarely needed. If the ROSC capacitor value is too large, the ROSC voltage reference will oscillate. 4.The VCC (23) bypass capacitor (0.1 F or greater) should be located as close as possible to the IC. This capacitor's connection to GND must be as short as possible. The most effective way to implement this tight component placement is to via the GATE1, 2, 3 and DRVON runs to internal layers right at the IC pins. 5.The switch nodes of all three phases must be sensed for inductive current sensing. Care should be given to how this information is brought to the CS5305. Switch node voltages should not be routed underneath or near the IC; however, the resistors in the RC filter of CS1, 2, 3 must be reasonably close to their associated capacitors so noise pick-up on the CS1, 2, 3 pins is minimized. The best solution is to locate the RC filter capacitors close to the CS1, 2, 3 pins and to place the respective resistors off to the side of the IC. 6.A positive temperature coefficient thermistor can be used for R11 (see Share Bus section) to compensate for thermal variation in the inductor ESR. This
component should be placed near the one of the inductors to achieve the best thermal coupling, and so the best current sharing performance. Remote placement with respect to the IC requires dedicated parallel runs of GND and IFB to reduce share bus noise sensitivity.
Thermal Considerations
Typically, the controller IC and the FET gate drivers do not dissipate significant amounts of power, and do not contribute greatly to module power dissipation. The main components of concern are the switch FETs and the inductors. We have already reviewed the power calculations for these components, but we haven't related them to a thermal solution. Standards exist limiting the maximum VRM printed circuit board temperature (105C is common), and thus power dissipation becomes a thermal consideration in addition to playing a part in overall module efficiency. Power dissipation on the VRM results in heat radiation to the surrounding air. Power dissipated by the components is conducted to the PCB. The PCB acts as a heat sink and provides a larger surface area for heat exchange to the surrounding air. The PCB temperature is dependent on total PCB power dissipation, the surface area of the PCB available to act as a heat sink, the ambient temperature of the surrounding air and the thermal resistance to ambient of the PCB. While it is possible to model power dissipation on the PCB for efficiency purposes, it is very difficult to accurately model thermal performance. In particular, thermal resistance to ambient of the PCB varies widely. This parameter depends on many factors: board shape, size and material; copper weight; amount of exposed copper; insulating characteristics of the solder mask layers; air flow properties (amount, direction, PCB orientation to the airflow); and even whether a particular component is "hidden" behind others. In reality, modeling PCB resistance to ambient is highly complex and the best way to guarantee thermal performance is to actually build prototypes and measure it directly.
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CS5305
Figure 50. Sample Layout Additional Information
Several additional resources are available to make system design with the CS5305 a simpler task. The power supply designer is invited to obtain the following documents and files from ON Semiconductor. 1.AND8045/D, "Enhanced V2 Multiphase SMPS for Microprocessor." This application note provides details on the theory of operation, selection of components, layout practices and thermal management strategies necessary to design power supplies with the CS5305 controller.
2."Excel Spreadsheet Method for Choosing CS5305 External Components". This Excel spreadsheet that can be used to generate a first-pass schematic design for VRM 9.x designs based on user input, and is available from the factory. 3."Excel Spreadsheet Method for CS5305 Power Budget Optimization". This Excel spreadsheet that can be used to calculate power dissipation in all the high-power dissipation components (including metal traces). This allows the design to be optimized for power/thermal management, and is available from the factory.
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CS5305
PACKAGE DIMENSIONS
SO-28L DW SUFFIX CASE 751F-05 ISSUE F
A D
28 15 M NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H L q MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0_ 8_
E
H
1 14 PIN 1 IDENT
B
A
0.25
M
B
e B 0.025
M
A1
0.10
SEATING PLANE
L
C q
C CA
S
B
S
Patents Pending. V2 is a trademark of Switch Power, Inc.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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CS5305/D

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